This invention relates generally to digital circuits. More particularly, it relates to an output buffer including control circuits for reducing power and/or ground bounce noise.
Digital logic circuits are widely used in the areas of electronics and computer-type equipment. One such use of digital logic circuits is to provide an interface function between one logic type (i.e., CMOS) of one integrated circuit device and another logic type (i.e., TTL) of another integrated circuit device. An output buffer is an important component for performing this interface function. The output buffer generates, when enabled, an output signal that is a function of a data input signal received from other logic circuitry of the integrated circuit.
An output buffer circuit typically uses a pull-up and a pull-down field-effect transistor coupled in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive potential which is coupled to an internal power supply potential node. The second power supply terminal may be supplied with a ground potential, which is coupled to an internal ground potential node. The connection point of the pull-up and pull-down field-effect transistors is further joined to an output terminal.
Dependent upon the logic state of the data input signal and an enable signal, either the pull-up or pull-down field-effect transistor is quickly turned on and the other transistor is turned off. Such rapid switching, on and off, of the pull-up and pull-down field-effect transistors causes sudden surges of current which create what is commonly known as current spikes. These current spikes flow through the impedance and inductive components of power supply lines and cause inductive noise at the internal power supply potential and the internal ground potential nodes of the output buffer. In particular, when the pull-down transistor is quickly turned on, a large instantaneous current cooperates with the line inductance to pull up the internal ground potential. This phenomenon is referred to as "ground bounce" noise. Similarly, when the pull-up transistor is quickly turned on, there may be "power bounce" noise on the internal power potential.
Therefore, it is desirable to provide a control circuit which limits the output current of the output buffer during transitions between logic states to reduce ground and/or power bounce noise, but yet maintains a high speed of operation. Further, it is desirable that the output buffer meets the DC specifications, such as the high output voltage (VOH) and the low output voltage (VOL) specifications.